As the size of planar transistors has been steadily decreasing since their inception, they are expected to suffer from undesirable short channel effects, especially in 32 nm and smaller technologies.
Conventional OTP (one time programmable) memory in MOS (Metal Oxide Silicon) generally takes advantages of thin-oxide breakdown, but experiences disadvantages, including unreliability for production. Because the heat generated in a P/N junction can easily be dissipated in a planar structure, spikes in the P/N junction that can be shorted due to dopant migration or inter-diffusion of contact alloy require extreme high current, such as an ESD (electrostatic discharge) zap, to reliably break the junction. An approach tying the gate with the drain and applying a high voltage to the source for using MOS as OTP is also unreliable.
Like reference symbols in the various drawings indicate like elements. The drawings are for illustration only and are not to scale.